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LOW POWER CLOCK GATING TECHNIQUE IN VLSI

By Admin on

INTRODUCTION TO CLOCK GATING:

                Clock gating is a well-known technique to reduce chip dynamic power. Recent  clock gating techniques based on ACG(Adaptive Clock Gating) and instruction level clock gating. clock gating technique reduces not only switching activity of functional blocks in IDLE state but also dynamic power in running state. Our modified ACG(Adaptive Clock Gating)  can automatically enable or disable the clock of the functional block. The experimental results on some I/O port core in SoC show an average of 19.45% dynamic power reduction comparing to previous ACG technique. Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree.




CLOCK GATING:

  • Everywhere acceptance of portable devices such as cell phones, PDAs and mp3 players has much research in the development of technique for low-power SOC.
  • The continuous decrease in the minimum feature size of transistors which increase of both device density and design complexity.
  •  The overall power dissipation on a chip is due to clock and data-path.
  • The clock -gating is one of the effective logic in RTL and architectural power reduction.
  • Clock gating is an effective technique to reduce dynamic power,because individual IP usage varies  across applications, not all IP cores are used all the time, giving rise to opportunity for reducing the unused IP cores’ power.
  • By combining(AND gate) the clock with a gate-control signal, clock gating essentially disables the clock to an IP core when that IP is not used, avoiding power dissipation due to unnecessary charging and discharging of the unused circuits.
  • The clock -gating is one of the effective logic in RTL and architectural power reduction. Clock gating is an effective technique to reduce dynamic power.

ACG(Adaptive Clock Gating):

  • DCG[Deterministic Clock Gating] is difficult to use to reduce power in the SOC[Silicon On Chip] design, which mainly integrates many separated IP cores by bus interconnections.
  • ACG(Adaptive Clock Gating)analyze the IP model first.
  • Any IP core (except combinational circuit) can be modeled as an Finite State Machine (FSM) which includes several states: Idle, Ready, Run and so on, as shown in the dashed box.


  • When an IP core finishes the work, it enters the idle state and stay there until it accepts another request from the system bus.
  • ACG disables the IP clock during the output signal is an active “high“ otherwise, the clock is enabled.

APPLICATIONS AND USES OF CLOCK GATING:

         Dynamic power management (DPM) has been very successful in low power design area. We used instruction level clock gating technique to control the clock of UART and I/O port. The clock gating efficiently reduces switching of the clock and register operation in the functional blocks.

CONCLUSION:

         By Using the instruction level clock gating and ACG, UART and I/O PORT are the  clock gating techniques which  is efficient for low power design in real SOC[SYSTEM ON CHIP].



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