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Low Power Scan-Based Testing in VLSI

By Admin on

SCAN BASED TESTING:

INTRODUCTION:

                 Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic.gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles.Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle.

               Design-for-testability (DFT) techniques have become an inseparable consideration for testing modern microelectronic designs as they play an important role in the improvement of the test quality and reducing the test application time in the VLSI digital circuits. The next generation of deep submicron circuits will rely not only on the low power VLSI design but also on the DFT methods targeting low power testing.

The problem of excessive power consumption during test application can mainly fall into two sub problems

     1)excessive average power consumption

     2) excessive peak power consumption


1)Excessive average power consumption:

 ---> This excessive average power consumption due to testing, in the first place, produces extra heat in CUT which has inevitable role in appearing hot spots, circuit premature destruction, degradation of performance, functional failures, and, as a result, circuit reliability degradation.

 --->The main mechanisms which lead to these structural degradations are corrosion (oxidizing of conductors),electro-migration (molecular migration of the conductor structure toward the electronic flow), hot-carrier-induced defects, or dielectric breakdown (loss of insulation of the dielectric barrier).

--->Excessive average power affects not only temperature increase but also temperature variations.

--->In addition, intensive heat generated by high switching activity during the test process has negative influences on the circuit packaging cost to make the CUT tolerable to higher level temperature.



 2) excessive peak power consumption:

--->Peak power is restricted to one clock period.

--->It restricting the time window to just one clock cycle is not realistic enough since the power consumption within one clock cycle may not be large enough to elevate the temperature over the thermal capacity limit of the chip.

--->The excessive noise may induce several phenomena


(1)Changing the logic value at some internal nodes of the circuit leads to failing of good dies and consequently unnecessary yield loss.

(2)Ground bounce or voltage droop: by increasing switching activities during test time, voltage glitches may be observed at some signal lines which can change rise/fall time of the gates (timing performance degradation) causing good dies to be declared “fail.”Thus, unwanted yield loss happens.

(3)IR-drop is referred to decrease (increase) in the power (ground) rail voltage and is linked to the existence of a non negligible resistance between the rail and each node in the CUT.

(4)Cross talk is referred to capacitive coupling between neighbouring nets within an IC. By increasing PSN, the voltage at some gates in the circuit is reduced (voltage drop) causing these gate to show higher delays (performance degradation), possibly leading to test fail and yield loss.



             


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