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POWER ANALYSIS OF VLSI DESIGN

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TRANSACTION-LEVEL POWER ANALYSIS OF VLSI DIGITAL SYSTEMS:

                                  The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation. Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques. In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.

1.INTRODUCTION:

  • Themain motivations behind these researches come from the need of design techniques at an abstraction level higher than register transfer level (RTL).
  • RTLtechniques are becoming less and less suitable to face the complexity reachedby many microelectronic products, as in the case of VLSI devices made up ofmillion of gates.
  • Moreprecisely, the evaluations conducted on RTL prototypes may be onerous in terms of execution times and design efforts, because it is necessary to work withrather detailed descriptions of the system architecture.
  • This can burden the design activities and make it difficult to meet strict time to-market constraints. On the other hand, ESL design techniques allow to work on systemprototypes derived from functional specifications, without having to deal withspecific implementation details. 
  • Thereare more chances to take major decisions in the early design phases and withlimited efforts, thus to speed up the flow towards the silicon implementation.Transaction level modeling (TLM) has established itself as an effective ESL paradigm, especially in the description of the communication tasks betweeninteracting modules.
  • A complex digital system composed by several interconnected modules, atransaction-level representation allows a good separation between communicationand elaboration tasks.             
  • The channel access is typically mediated by calls tointerface functions capable to transport consistent data amount; each module is independent from the others with regard to interconnectivity.
  • Themain benefits due to these features consist in the use of system prototypesthat can be defined and simulated in reduced times
  • Moreover,the high interoperability of transaction-level models facilitates the realization of complex system architectures.
  • Nowadays,power performances are often a crucial constraint in the design of VLSI digitalsystems, in consequence of the wide diffusion of battery-supplied devices aswell as the reliability issues due to high clock frequencies.
  • The estimation of power dissipation is by now a primary design matter, providing useful indications in the analysis of implementation options and low-power solutions.
  • Power estimation on RTL representations has been extensively studied, and a number of effective and well-tested techniques.
  • First case, the power estimation is achieved by evaluating a power model at the end of a simulation period, on the basis of average input statistics.
  • cycle-accurate technique leads to evaluate the power model at every time cycle, requiring as input data cycle-based quantities.
  • For a specific CMOS technology, such characterization may be carried out once and for all, and the results may be reused for several VLSI systems based on that technology. 
  • Finally,once built the power models of the basic modules, we can perform power estimations on the whole system in its RTL representation.
  • In particular, power estimations on transaction-level representationsconstitute an attractive investigation field that needs to be explored more deeply

      Fig 1.Transaction Level Modeling


2.Modeling principles of SystemC/TLM:

  • SystemC/TLM has been developed as an extension of the SystemC core language, with the aim to optimize the semantics and thesimulation capabilities for transaction-level representations.
  • In a typical RTL representation the inter-module communi-cationsare realized through wire-like connections, pin-accurate I/O ports and clock-synchronized data transfers. Such scenario changes dramaticallywhen moving to a SystemC/TLM description, in which the inter module connections are virtually replaced by transport interfaces and the time references are restricted to the duration of transaction phases.
  • More precisely,a transaction is modeled by means of calls to TLM functions thatexecute consistent data exchange between an initiator and a targetmodule. The function calls may proceed from initiator to target(forward path) or in the reverse way (backward path).
  • In alternative mode, the modules involved in a TLM functioncall may be identified as caller and callee. The caller issues the functioncall, whereas the callee deals with the function execution according toa customized definition. The distinction between caller and callee isindependent from the logical roles covered by a module as initiator.
  • The data exchanged in a transaction are typically referred to theformat of a digital communication protocol.
  • SystemC/TLM makes available a protocol template, called generic payload,suitable for memory-mapped bus (MMB) protocols and conceived toguarantee a high interoperability among models coming from different parts.
  •  However, generic payload includes some flexibility elementsfor a possible adaptation to specific communication protocols.

Fig.2.SystemC/TLM




                                                   

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