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A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
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A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL14


Project Abstract

Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less Area Delay Product (ADP) and less Energy Per Sample (EPS) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. Application Specific Integrated Circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves] 42% less ADP and 40% less EPS than the best available FIR filter structure proposed for reconfigurable applications. For the same filter length and the same block size, the proposed structure involves 13% less ADP and 12.8% less EPS than that of the existing direct-form blocks FIR structure.

 

EXISTING SYSTEM

PROPOSED  SYSTEM

EXISTING CONCEPT :          

·         The existing work on the realization of FIR filter provides block performance the input sample and the response multiplied in that i limits only get altered n assigned to value at each determination of the output data flow graphs shows the process occurs in each block. Assigning of values is seems to be difficult while doing transformation of the outputs in those configurations.   

PROPOSED CONCEPT :  

·         In this proposed we have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters.

EXISTING TECHNIQUE:

        Direct-form realization.

PROPOSED TECHNIQUE:

         Realization of block FIR filter in transpose form configuration

TECHNIQUE DEFENITION: 

         Direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure..

TECHNIQUE DEFENITION: 

         Realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications.

DRAWBACKS:

         It provides only block performance.       

        Delay, Area high.

 

ADVANTAGES:

         Block and higher order N  processing.

 

        Less area requirement, Low delay.


 
 
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