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An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders
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An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL36


Project Abstract

Approximate adders have been considered as a potential alternative for error-tolerant applications to trade off some accuracy for gains in other circuit-based metrics, such as power, area and delay. Existing approximate adder designs have shown substantial advantages in improving many of these operational features. However, the error characteristics of the approximate adders still remain an issue that is not very well understood. A simulation-based method requires both programming efforts and a time-consuming execution for evaluating the effect of errors. This method becomes particularly expensive when dealing with various sizes and types of approximate adders. In this paper, a framework based on analytical models is proposed for evaluating the error characteristics of approximate adders. Error features such as the error rate and the mean error distance are obtained using this framework without developing functional models of the approximate adders for time-consuming simulation. As an example, the estimate of peak signal-to-noise ratios (PSNRs) in image processing is considered to show the potential application of the proposed analysis. This analytical framework provides an efficient method to evaluate various designs of approximate adders for meeting different figures of merit in error-tolerant applications.

 

 

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

      The ACA utilizes insufficient information, i.e., k LSBs for predicting the sum of each bit in an n-bit adder (n > k). The same illustration as in is used for the ACA (and the ESA in the following section). Bits  (i.e., k ¼ 4) are used to calculate each bit in the sum of an n-bit adder. The identical vertical rectangular blocks on the top denote the inputs, while the horizontal rectangles under them show the carry propagation paths for each sum bit. This design is based on the observation that the carry propagation chain is usually shorter than n

PROPOSED CONCEPT:           

          The ETAII is also based on the truncation of the carry propagation chain and the segmentation of a full-sized adder. Compared to the ESA, the predicted carry input for each segmented k-bit sub-adder (or the sum generator) is generated by k LSBs. The ETAII has an improved accuracy compared to the ESA, because it uses more information to predict the carry when the same k is used. In the so-called speculative carry select addition (SCSA), an n-bit adder is first divided into n k sub-adders each sub-adder consists of two k-bit adders

EXISTING TECHNIQUE:

         ASA

PROPOSED TECHNIQUE:

         ETAII

TECHNIQUE DEFINITION:

         It is based on the observation that the carry propagation chain is usually shorter than n, i.e. in practice, the truncation of the chain up to some

length has a very low probability to be erroneous

TECHNIQUE DEFINITION:

         It is also based on the truncation of the carry propagation chain and the segmentation of a full-sized adder

DRAWBACKS:

         length has a very low probability

         The truncation of the chain up

         Erroneous results

ADVANTAGES:

         The approximate adders also have an error correction circuit that permits an additional accurate operation mode

         The accuracy-configurable approximate adder propose can adjust the accuracy


 
 
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