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An Efficient Constant Multiplier Architecture Based on Vertical Horizontal Binary Common Sub expression Elimination Algorithm for Reconfigurable FIR Filter
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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter

Category : VLSI


Project Code : ITVL02

Project Abstract

In this paper we propose an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. Faithfully rounded truncated multiple constant multiplication/accumulation MCMAT) and multi root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.





        The existing system based on 2 and 3 bit BCSE algorithm that expresses   multiplying the input(X) and the coefficient (H) partial products are generated and each bit is allowed through 4:1 multiplexers and addition shift operation takes place. The several adders are used to add the generated multiplexers output. At final a 2:1 multiplexer used to generates the 16 bit output.


         In this system we used vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm states that to manipulate the 16 bit input by layered operation.  At initial the coefficient is coded to applicable for negative decimal numbers also ie.taking 2’s complement for coefficient and the partial products generated by alternate method and controlled additions are used to produce output efficiently.


     2-bit BCSE algorithm.

     3- bit BCSE algorithm.


         Vertical-Horizontal Binary Common Sub-expression Elimination (VHBCSE) algorithm.


         2-bit BCSE algorithm is a method of assigning the values that existing in the sequence by leaving the upcoming two bits of each bit.

         3-bit BCSE algorithm is a method of assigning the values that existing in the sequence by leaving the upcoming three bits of each bit.


         A 2-bit vertical BCSE has been applied first on the adjacent coefficient, followed by 4-bit and 8-bit horizontal BCSEs to detect and eliminate which are present within each of the coefficient.

         This   can work for signed decimal number of both the input and the coefficients along with a reduced probability of use of the adders to sum up the partial product generator by extending the BCSE at the lower level.


         Number of multiplexers used is high hence large area required.      

         Delay is high due to process of every bit.


         Number of multiplexer used is less.

         Less area requirement, Low delay.

         Multiplier switching activities get reduced.

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