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Analysis and Design of a Low Voltage Low Power Double Tail Comparator
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Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL32


Project Abstract

The need for ultra low-power, area efficient, and high speed analog-to-digital converters  is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. Designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced.

 

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

·         Clocked regenerative comparators have found wide applications in many high-speed ADCs since they can make fast decisions due to the strong positive feedback in the regenerative latch.

 

·          Recently, many comprehensive analyses have been presented, which investigate the performance of these comparators from different aspects.

PROPOSED CONCEPT:

·         The proposed dynamic double-tail comparator. Due to the better performance of double-tail architecture in low-voltage applications, the proposed comparator is designed based on the double-tail structure.

          The main idea of the proposed comparator is to increase _Vfn/fp in order to increase the latch regeneration speed.

EXISTING TECHNIQUE:

·         Conventional Dynamic Comparator and Conventional Double-Tail Dynamic Comparator

 

PROPOSED TECHNIQUE:

·         Proposed dynamic double-tail comparator

TECHNIQUE DEFENITION:        

·         The conventional dynamic comparator widely used in A/D converters, with high input impedance, rail-to-rail output swing, and no static power consumption

 

TECHNIQUE DEFENITION:        

·         A new dynamic comparator with low-voltage low-power capability was proposed in order to improve the performance of the comparator.

DRAWBACKS:

·         High voltage

·         High power

 

ADVANTAGES:

         Low voltage

         Low power

 


 
 
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