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Coplanar Full Adder in Quantum Dot Cellular Automata via Clock Zone Based Crossover
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Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL19


Project Abstract

We use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. This crossover uses non-adjacent clock zones for the two crossing wires. We further investigate the impact of these gains on carry flow QCA adders. These designs have been realized with QCA Designer, evaluated, and tested for correctness. For better performance comparison with previous relevant works, we use a QCA-specific cost function, as well as the conventional evaluation method. We show 23% cell count and 48% area improvements over the best previous QCA full adder design. Similar results for 4-, 8-, 16-, 32-,,and 64-bit adders are 29% (22%), 24% (51%), 19% (54%), 13% (69%), and 9%(49%) cell count reduction (less area consumption), respectively.

 

EXISTING SYSTEM

PROPOSED SYSYEM

EXISTING CONCEPT:

        We have presented an efficient QCA design for an n-bit ripple carry adder and various prefix adders. We have shown that the proposed ripple carry adder has substantially lower area and delay than existing RCA designs.

     We have also shown that the Brent–Kung adder has lower delay than all other adder designs studied here (and in prior work) for large word sizes. Further, the Brent– Kung adder performs best among the prefix adders in terms of delay and area.

PROPOSED CONCEPT:

Ripple carry QCA adder:

      The first QCA adder that we have encountered is due to where a straightforward n-bit ripple carry adder is realized via cascading n QFAs.

Carry flow adders:

     This is basically the same as the previous design, except for the cin–cout delay that is reduced to ¼ clock cycle.

Parallel prefix QCA adders:

     Straightforward realization of parallel prefix QCA adders would implement the group generate, propagate, and carry signals, based on QCA AND and OR gates, with total of two QMs per parallel prefix node.

EXISTING TECHNIQUE:

         Brent–Kung Adders in QCA

PROPOSED TECHNIQUE:

         Clock-Zone Based adder in QCA

DRAWBACKS:

·         Speed less

·         More number of gate count taken for in our operation because this is micrometer technology.

ADVANTAGES:

         Speed high

·         Less number of gate count taken for in our operation because this is nanometer technology.


 
 
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