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Efficient coding scheme for fault Tolerant parallel filter
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Efficient coding scheme for fault Tolerant parallel filter

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL37


Project Abstract

As the complexity of communications and signal processing systems increases, so does the number of blocks or elements that they have. In many cases, some of those elements operate in parallel performing the same processing on different signals. A typical example of those elements are digital filters. The increase in complexity also poses reliability challenges and creates the need for fault tolerant implementations. A scheme based on error correction coding has been recently proposed to protect parallel filters. In that scheme, each filter is treated as a bit and redundant filters that act as parity check bits are introduced to detect and correct errors. In this paper, the idea of applying coding techniques to protect parallel filters is addressed in a more general way. In particular, it is shown that the fact that filter inputs and outputs are not bits but numbers enables a more efficient protection. This reduces the protection overhead and makes the number of redundant filters independent of the number of parallel filters. The proposed scheme is first described and then illustrated with two case studies. Finally, both the effectiveness in protecting against errors and the cost are evaluated for an FPGA implementation.

PROPOSED SYSTEM:

             The input signals are encoded using a matrix with arbitrary coefficients to produce the signals that enter the four original and two redundant filters. In a practical implementation, the first four rows of the matrix would be an identity matrix so that the inputs With this coding scheme, the outputs of the filters, y1[n], y2[n], y3[n], y4[n]. This process can be repeated with different sub-matrixes of A, for example with A1236, A2345, A2346. In the error free case, all the recovered versions of y1[n], y2[n], y3[n], y4[n] will be the same.

              The error correction and detection logic can be simplified assuming that there is only a single error. In that case, checking only that for each recovered set the sums of the values: y1[n]+ y2[n]+y3[n]+ y4[n] are equal is enough. The complexity of the error detection and correction relies on the design of A. For a practical implementation, the first four filter outputs (z1[n], z2[n], z3[n], z4[n]) should be equal to the final filters outputs (y1[n], y2[n], y3[n], y4[n]) in order to avoid additional computations to reconstruct those outputs.
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