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Energy and Area Efficient Three Input XOR/XNORs With Systematic Cell Design Methodology
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Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Category : VLSI


Sub Category : EDA TOOL (TANNER TOOL)


Project Code : ITVL27


Project Abstract

In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%–77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%–32% improvement in area is demonstrated.

 

EXISTING SYSTEM

PROPOSED SYSTEM

 

EXISTING CONCEPT:

         XO7 and XO8 model are predefined but their outputs have more noise and inefficient because they require more space and power .

         XO7 three input XOR AND XOR gate have more compact space and require less power compared with XO8

 

PROPOSED CONCEPT:           

         Our Proposed system deals with minimizing the area and power required by three input XOR AND XNOR gate and mainly focuses on obtaining the perfect output without noise. Our proposed XO4 delay mainly depends on data-dependency.

 

EXISTING TECHNIQUE:

        Transistor Switching

 

PROPOSED TECHNIQUE:

         Gates signal switching

 

TECHNIQUE DEFINITION:

         Each logic functions switches are switched from each active transistor

 

TECHNIQUE DEFINITION:

·         Here the logic functions are switched by gate active signal

 

DRAWBACKS:

         External vdd is required for each transistor is switched on.

 

ADVANTAGES:

·         Less area overhead system

         Less power consumption

         High speed architecture


 
 
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