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Exact and Approximate Algorithms for the Filter Design Optimization Problem
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Exact and Approximate Algorithms for the Filter Design Optimization Problem

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL09


Project Abstract

The filter design optimization (FDO) problem is defined as finding a set of filter coefficients that yields a filter design with minimum complexity, satisfying the filter constraints. It has received a tremendous interest due to the widespread application of filters. Assuming that the coefficient multiplications in the filter design are realized under a shift-adds architecture, the complexity is generally defined in terms of the total number of adders and subtractors. In this paper, we present an exact FDO algorithm that can guarantee the minimum design complexity under the minimum quantization value, but can only be applied to filters with a small number of coefficients. We also introduce an approximate algorithm that can handle filters with a large number of coefficients using less computational resources than the exact FDO algorithm and find better solutions than existing FDO heuristics. We describe how these algorithms can be modified to handle a delay constraint in the shift-adds designs of the multiplier blocks and to target different filter constraints and filter forms. Experimental results show the effectiveness of the proposed algorithms with respect to prominent FDO algorithms and explore the impact of design parameters, such as the filter length, quantization value, and filter form, on the complexity and performance of filter designs.


 

EXISTING SYSTEM

PROPOSED  SYSTEM

EXISTING CONCEPT :     

·         In Existing Design Wallace and modified Booth multipliers, have been proposed, the full flexibility of a multiplier is not necessary for the constant multiplications, since filter coefficients are fixed and determined beforehand by the DSP algorithms. Hence, the multiplication of filter coefficients with the input data is generally implemented under shift adds architecture, where each constant multiplication is realized using addition/subtraction and shift operations in an MCM operation.

PROPOSED CONCEPT :

·         In this proposed system, we initially determine the gate-level implementation costs of digit-serial addition, subtraction, and left shift operations used in the shift-adds design of digit-serial MCM operations. Then, we introduce the exact CSE algorithm that formalizes the gate-level area optimization problem as a 0–1 integer linear programming problem when constants are defined under a particular number representation.

EXISTING TECHNIQUE:

·         Partial product sharing

PROPOSED TECHNIQUE:

        Exact CSE algorithm

         Exact GB algorithm

TECHNIQUE DEFENITION: 

·         The Partial Products Method helps simplify long multiplication. It is a very accessible method because it breaks down complex numbers into simpler, more easily-multiplied, ones.

TECHNIQUE DEFENITION: 

         The CSE and GB are  the shortest constant multipliers used to design the FIR filter.

DRAWBACKS:

·        Its occupied area, delay are high.

ADVANTAGES:

         Area ,Delay and Power-efficient

 

 
 
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