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High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
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High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL01


Project Abstract

       In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is

achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

 

 

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

         Conventional CSKA is a RCA-RCA configuration which generates a pair of sum words and output-carry bits corresponding the anticipated input-carry  (cin= 0 and 1), and selects one out of each pair for final-sum and final-output-carry.

        Conventional CSKA has less CPD than RCA, but the design is not attractive, since it uses dual RCA. Few attempt have been made to avoid dual use of RCA in CSKA design.

PROPOSED CONCEPT:           

         The CBL based CSKA of  involves significantly less logic resource than the conventional CSKA, but it has longer CPD which is almost equals to that of RCA. To overcome this problem, SQRT-CSKA based on CBL have been proposed.

         We observe that, logic optimization largely depends on availability of redundant operations in the formulation, where adder delay mainly depends on data-dependency.

EXISTING TECHNIQUE:

       Ripple Carry Adder

PROPOSED TECHNIQUE:

         New Carry skip Adder

TECHNIQUE DEFINITION:

        A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the succeeding next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage.

TECHNIQUE DEFINITION:

·         This technique is used for the next stage of the binary output.

DRAWBACKS:

       More area overhead system

         More power consumption

       Low speed architecture

ADVANTAGES:

       Less area overhead system

        Less power consumption

        High speed architecture

 

 
 
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