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Implementation of Sub threshold Adiabatic Logic for Ultralow Power Application
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Implementation of Sub threshold Adiabatic Logic for Ultralow-Power Application

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL07


Project Abstract

Behavior of adiabatic logic circuits in weak inversion or sub threshold regime is analyzed in depth for the first time in the literature to make great improvement in ultra low power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on sub threshold adiabatic logic-based 4-bit CLA has also been addressed separately. Post layout simulations show that sub threshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.

 

EXISTING SYSTEM

PRPOSED SYSTEM

EXISTING CONCEPT:

            A CMOS  transistor (or device) has four terminals: gate, source , drain , and a fourth terminal that we shall ignore until the next section. A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals (using open and closed for switches is confusing—for the same reason we say a tap is on and not that it is closed ). The transistor source and drain terminals are equivalent as far as digital signals are concerned—we do not worry about labeling an electrical switch with two terminals.

PROPOSED SYSTEM:

           In adiabatic logic circuits, ramp type supply voltage is used to slow down the charge transport mechanism. Hence, the supply clock plays the pivotal role. A ramp type supply voltage φ(t) is considered in Fig. 1(a), which gradually swings in between logic 0 (Gnd potential) and logic 1 (VDD) in time duration 2T, where f (=1/2T ) is the supply clock’s frequency. The power supply waveform φ(t) can be divided into charging phase, when φ(t) ramps up from 0 to VDD in 0 to T unit time and discharging phase when φ(t) ramps down from VDD to 0 in T to 2T unit time.

EXISTING TECHNIQUE:

         Normal CMOS Logic

PROPOSED TECHNIQUE:

         SAL Adiabatic Logic

TECHNIQUE EXPLANATION:

       If Vin is down (0 volts), NFET is OFF and PFET is ON pulling Vout to Vdd (high = 1)

      If Vin is up (at Vdd), NFET is ON hard and PFET is OFF pulling Vout low to Gnd (“0”)

TECHNIQUE EXPLANATION:

                 The design as in SAL basic logic gates have been implemented using either the pull-up or the pull-down transistors. Therefore,

the SAL-based CLA is also area efficient in comparison with the conventional structure.

DRAWBACKS:

         Number of transistor large.

         Power is high

ADVANTAGES:

         Number of transistor less

         Power is less

 


 
 
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