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EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

·         Binary addition is the single most important operation that a processor performs.

·         Most of the adders have been designed for synchronous circuits even though there is a strong interest in clock less / asynchronous processors /circuits.

PROPOSED CONCEPT:

         The architecture and theory behind PASTA is presented. The adder first accepts two input operands to perform half additions for each bit.

        Subsequently, it iterates using earlier generated carry and sums to perform half-additions repeatedly until all carry bits are consumed and settled at zero level.

EXISTING TECHNIQUE:

·         Delay Insensitive Adders Using Dual-Rail Encoding

PROPOSED TECHNIQUE:

·         parallel single-rail self-timed adder

TECHNIQUE DEFENITION:        

·         In an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level of change of a special signal called as the clock.

TECHNIQUE DEFENITION:        

·         Self-timed adders have the potential to run faster averaged for dynamic data, as early completion sensing can avoid the need for the worst case bundled delay mechanism of synchronous circuits.

DRAWBACKS:

·        Expensive

·        Little complex

·        Slower circuit

ADVANTAGES:

         Low cost

         Very simple

         Faster