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Trade offs for Threshold Implementations Illustrated on AES
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Trade-offs for Threshold Implementations Illustrated on AES

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL03


Project Abstract

      Embedded cryptographic devices are vulnerable to power analysis attacks. Threshold Implementations provide provable security against first-order power analysis attacks for hardware and software implementations. Like masking, the approach relies on secret sharing but it differs in the implementation of logic functions. While masking can fail to provide protection due to glitches in the circuit, Threshold Implementations rely on few assumptions about the hardware and are fully compatible with standard design flows. We investigate two important properties of Threshold Implementations in detail and point out interesting trade-offs between circuit area and randomness requirements. We propose two new Threshold Implementations of AES that, starting from a common previously published implementation, illustrate possible trade-offs. We provide concrete ASIC implementation results for all three designs using the same library, and we evaluate the practical security of all three designs on the same FPGA platform. Our analysis allows us to directly compare the security provided by the different trade-offs, and to quantify the associated hardware cost. 

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

RAW IMPLEMENTATION:

        This TI of the S-box (details will be given in the following section) requires four input shares, therefore we initially share the plaintext in four shares. We share the key in two shares and XOR them with two of the plaintext shares before the S box operation. More details about the key scheduling will be given later in this section.

ADJUSTED IMPLEMENTATION:

          Each of the existing three shares is XORed with a random byte and the sum of these random bytes is taken as the fourth share. This also ensures uniformity of the S-box input. Together with the state, the number of shares for Mix Columns and Key XOR increases to three.

PROPOSED CONCEPT:

NIMBLE IMPLEMENTATION:

        Similar to the raw implementation, this one also uses two shares for the state and key arrays. The main difference is that the S-box needs three input shares instead of four. Hence the size of the register P0 is reduced to 8-bits (one share). As a result, we need only 16- bits of randomness to increase the number of shares from two to three before the S-box operation, i.e. each share is XORed with one byte of randomness and the XOR of the random bytes is taken as the third share.

EXISTING  ALGORITHM:

·         Raw implementation

·         Adjusted implementation

PROPOSED  ALGORITHM:

         Nimble implementation

ALGORITHM  DEFINITION:

      we need 44 fresh random bits per S-box operation including increasing the number of shares of the Sbox input.

      we use 24-bits of randomness to increase the number of shares from three to four one cycle before the S-box,

ALGORITHM  DEFINITION:

      This construction requires only 32-bits of extra randomness per S-box calculation, including increasing the number of shares for the S-box input.

EXISTING SYSTEM DRAWBACKS:

·         The longest critical path

·         The maximum area of occupancy

·         Low speed

ADVANTAGES:

         Area efficient

         High Throughput

         More Secure


 
 
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