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Ultralow Energy Variation Aware Design: Adder Architecture Study
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Ultralow-Energy Variation-Aware Design: Adder Architecture Study

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL10


Project Abstract

Power consumption of digital systems is an important issue in nano scale technologies and growth of process variation makes the problem more challenging. In this brief, we have analyzed the latency, energy consumption, and effects of process variation on different structures with respect to the design structure and logic depth to propose architectures with higher throughput, lower energy consumption, and smaller performance loss caused by process variation in application specific integrated circuit design. We have exploited adders as different implementations of a processing unit, and propose architectural guidelines for finer technologies in sub threshold which are applicable to any other architecture. The results show that smaller computing building blocks have better energy efficiency and less performance degradation because of variation effects. In contrast, their computation throughput will be mid or less unless proper solutions, such as pipelined or parallel structures, are used. Therefore, our proposed solution to improve the throughput loss while reducing sensitivity to process variations is using simpler elements in deep pipelined designs or massively parallel structures.

 

 

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

          In KSA, addition is performed with higher speed because of parallel computations in shorter paths with only log2 N logic stages besides higher area overhead. Han–Carlson adder (HCA) is a combination of  BKA and KSA to reduce the complexity and make a tradeoff between area and delay with log2 N+1 logic stages. Another prefix adder which has minimum logic depth (log2 N) is known as Lander–Fisher adder (LFA).

PROPOSED SYSTEM:

            Serial full adder (SFA) is a basic full adder which is combined with a flip-flop to utilize the adder unit at different clock cycles in time-serialized ripple-carry manner  and the number of clock cycles that it takes is equal to the number of bits. In addition, the area of RCA structure is the lowest among more complex ones and is almost 16 times bigger than serial single full adder (SFA).

EXISTING TECHNIQUE:

         KSA,LFA,BKA,RCA

PROPOSED TECHNIQUE:

         Serial Full adder

TECHNIQUE DEFINITION:

        This technique are different type of full adder.

TECHNIQUE DEFINITION:

        Serial full adder (SFA) is a basic full adder which is combined with a flip-flop to utilize.

DRAWBACKS:

        Number of gate counts is high

         Delay is high

ADVANTAGES:

         Number of gate counts is low

         Delay is less

 


 
 
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