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EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

·         Methodologies for the synthesis of MVL digital circuits comprise of the operators and their properties. Main drawbacks of such methodologies are: first, the lack of     existing integrated circuits that implement the universal set of gates and, second, minimization tools needed to design practical MVL digital circuits.

PROPOSED CONCEPT:

·         For the user, the environment should be easy to learn, convenient (adequate to use in hybrid binary-MVL systems), be reliable, and fast. the design and implementation of a universal set of IC gates based on the CMOS 0.35 μm technology, comprised of extended AND operators: eAND1, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to allow synthesis of MVL digital circuits and the implementation of the circuits that are the basis to build the gates. The design methodology will be applied to the synthesis of MVL multiplexer and latch memory circuits to illustrate utilization of the proposed ICs.

EXISTING ALGORITHM:

·         digital circuits

PROPOSED ALGORITHM:

         Universal sets of MVL CMOS gates

ALGORITHM DEFINITION:

·         The synthesis of digital circuits is performed in the well known two level logic (N=2) switching algebra, D={0,1}.

ALGORITHM DEFINITION:

·         By increasing the domain of the digital representation to levels (D=0, 1, 2… N-1), it is possible to design Universal sets of MVL (Multiple Valued Logic) circuits.

EXISTING SYSTEM DRAWBACKS:

·         Low Throughput

·         Area Increased

PROPOSED SYSTEM ADVANTAGES:

         High Throughput and Low area

         Hardware efficiency