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Project Zone > Electronics > VLSI

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata.

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL22


Project Desc : Turbo encoding is one of such applications, which refers to three representative issues of bit-serial circuits: convolution computation, feedback, and serial data permutation. The inherent shift-register nature of QCA offers an advantage to performing convolution computation but poses handicaps to resolve the latter two issues.

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Area-Delay Efficient Binary Adders in QCA.

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL23


Project Desc : Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators.

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Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

Category : VLSI


Sub Category : DESIGN with TEST BENCH


Project Code : ITVL24


Project Desc : As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward.

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ERSFQ 8-Bit Parallel Adders as a Process Benchmark

Category : VLSI


Sub Category : DESIGN with TEST BENCH


Project Code : ITVL25


Project Desc : The VLSI implementation results show a significant delay reduction and area time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in nowadays systems.

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(4 + 2log n)ΔG Parallel Prefix Modulo-(2n − 3) Adder via Double Representation of Residues in [0, 2]

Category : VLSI


Sub Category : DESIGN with TEST BENCH


Project Code : ITVL26


Project Desc : The problem of static power dissipation in RSFQ (Rapid Single-Flux-Quantum) logic has been discussed since its invention . It was widely perceived at the time, that solving this problem was not very urgent while demonstrating small scale devices. With the maturity of RSFQ technology, elimination of static power dissipation has become a very important problem.

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Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Category : VLSI


Sub Category : EDA TOOL (TANNER TOOL)


Project Code : ITVL27


Project Desc : In this brief, we propose the fastest of such adders, where residues in {0, 1, 2} can be represented also as excess-(2n ? 3) encoding (i.e., {2n ? 3, 2n ? 2, 2n ? 1}, respectively). The delay and area overhead of the proposed adder with respect to the base modulo-(2n ? 1) adder is only one extra gate in the critical delay path and, at most, 20% more area.

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Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Category : VLSI


Sub Category : EDA TOOL (TANNER TOOL)


Project Code : ITVL28


Project Desc : A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel.

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Recursive Approach to the Design of a Parallel Self-Timed Adder

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL29


Project Desc : A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing.

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Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL30


Project Desc : Finite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping FSMs into ROM memory. In this paper, we propose a new architecture for implementing FSMIMs, called FSMIM with state-based input selection, whose goal is to achieve a further reduction in memory usage.

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Finite State Machines With Input Multiplexing: A Performance Study

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL31


Project Desc : Based a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened.

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