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Project Zone > Electronics > VLSI

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL01


Project Desc : The main concept of this paper is deal with removing the carry propagation delays of the additions in the processors. This latest modulation scheme reduces the area of the microprocessor for holding the carry values of the registers. So it preferably reduces the voltage consumption of the processors.

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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL02


Project Desc : In this paper we propose an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time.

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Trade-offs for Threshold Implementations Illustrated on AES

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL03


Project Desc : We investigate two important properties of Threshold Implementations in detail and point out interesting trade-offs between circuit area and randomness requirements. We propose two new Threshold Implementations of AES that, starting from a common previously published implementation, illustrate possible trade-offs.

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A Modified Partial Product Generator for Redundant Binary

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL04


Project Desc : Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.

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Reviewing High-Radix Signed-Digit Adders

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL05


Project Desc : Radix multipliers are more prominent adders, the present world is hanging through the latest and fast refined multiplication. This paper is to enhance the speed of recoding the multiplier in the best way as easy as possible. The radix is recoded for 4r^2.

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Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm

Category : VLSI


Sub Category : AREA EFFICIENT


Project Code : ITVL06


Project Desc : From the critical-path evaluation, it is further shown that no pipelining is required for implementing a direct-form LMS adaptive filter for most practical cases, and can be realized with a very small adaptation delay in cases where a very high sampling rate is required.

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Implementation of Sub threshold Adiabatic Logic for Ultralow-Power Application

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL07


Project Desc : The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on sub threshold adiabatic logic-based 4-bit CLA has also been addressed separately.

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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL08


Project Desc : Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier.

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Exact and Approximate Algorithms for the Filter Design Optimization Problem

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL09


Project Desc : We also introduce an approximate algorithm that can handle filters with a large number of coefficients using less computational resources than the exact FDO algorithm and find better solutions than existing FDO heuristics.

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Ultralow-Energy Variation-Aware Design: Adder Architecture Study

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL10


Project Desc : In contrast, their computation throughput will be mid or less unless proper solutions, such as pipelined or parallel structures, are used. Therefore, our proposed solution to improve the throughput loss while reducing sensitivity to process variations is using simpler elements in deep pipelined designs or massively parallel structures.

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